Automated patching techniques to correct certain rule violations are used,
simplifying and automating the design layout of an electronic circuit, whether
embodied as a design encoding or as a fabricated electronic circuit. A series of
patches of predefined orientations are utilized to correct design rule violations.
A set of violations are identified, patches of a predefined orientation are attempted
to correct one or more violations. Patches of another predefined orientation are
attempted to correct remaining violations. Attempted patching is repeated until
all patches in the series have been attempted or all violations have been corrected.
Patches can be added to a construction layer over the set of violations, and each
patch that does not cause a design rule violation can be copied to a metal layer.
A series of patches of predefined orientations are used, efficiently correcting
design rule violations such as minimum area and jog rule violations.
