A memory controller controls a buffer which stores the most recently used addresses
and associated data, but the data stored in the buffer is only a portion of a row
of data (termed row head data) stored in main memory. In a memory access initiated
by the CPU, both the buffer and main memory are accessed simultaneously. If the
buffer contains the address requested, the buffer immediately begins to provide
the associated row head data in a burst to the cache memory. Meanwhile, the same
row address is activated in the main memory bank corresponding to the requested
address found in the buffer. After the buffer provides the row head data, the remainder
of the burst of requested data is provided by the main memory to the CPU.
