An on-chip calibration circuit which can dynamically (i.e., in operational environment)
measure the capacitor mismatch in an ADC using sampling capacitors to sample an
input signal and a feedback capacitor (in combination with an amplifier) for amplification.
The measured values can be used to generate accurate digital codes representing
analog signal samples. The calibration circuit connects the capacitors to various
voltage levels and measures the mismatch levels by examining various signals (e.g.,
the digital codes) generated in such situations.
