Embodiments of the present invention provide for implementation of data
transfers in an efficient manner. The 48-bit LBA mechanism requires two sets of
I/O writes to IDE registers on primary channel or secondary channel. The two sets
of I/O writes to the primary or secondary channel registers are performed by setting
a status register to a first or second state appropriately depending on the data.
Embodiments of the present invention provide a single set of writes to I/O registers
when the size of the data transfer is equal to or below a threshold value.
