Trace control circuit for tracing CPU operation in real time

   
   

A trace control circuit includes a branch event generation circuit 1 having an address abbreviation information generation circuit 8 for detecting a portion in which a branch-source address and a branch-destination address are overlapped with each other from the upper-bit side of the address data thereof and generating branch-destination address abbreviation information on the basis of the result of the detection, and a trace data abbreviation circuit 5 for performing abbreviation of one part of trace data in accordance with the branch-destination address abbreviation information and outputting the partly abbreviated trace data, whereby the number of data packets of the trace data can be reduced to speed up the output operation of the trace data, and the ability to output trace data in real time can be thereby improved greatly.

 
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