A delay optimization algorithm has four major steps: (1) selecting signal connections
to target for delay improvement; (2) unrouting all signals containing those candidate
connections; (3) rerouting those signals, using a "load-balancing"heuristic; and
(4) during rip-up and re-try routing, protecting wiring to all signal loads routed
by the heuristic, including non-timing critical loads. Load balancing includes
(a) applying a branching penalty on logic cell output wire segments, and (b) encouraging
all non-route critical loads to route through a single buffered wire segment.
