The present invention provides a network device including a central timing
subsystem for distributing one or more timing reference signals including
a main timing signal and an embedded timing signal. Embedding one timing
signal within another reduces the routing resources necessary to route the
timing signal(s) within the network device. In addition, one central
timing system, as opposed to two or more, may be used to provide multiple
different synchronous clock signals. In one embodiment, the main timing
signal is used for network data transfer while the embedded signal is used
at least for processor synchronization. Consequently, a separate central
timing subsystem is not required for generation and distribution of
processor timing reference signals, and separate routing resources are not
required for the processor timing reference signals. In addition, separate
local timing subsystems for both the central timing and processor timing
are not necessary. Embedding the processor timing reference signal within
a highly accurate, redundant external timing reference signal also
provides a highly accurate and redundant processor timing reference
signal, and having a common local timing subsystem is more efficient
resulting in less design time, less debug time, less risk, design re-use
and simulation re-use.
