Circuits and methods for generating high frequency extended test pattern data from low frequency test pattern data input to an integrated circuit memory device

   
   

An integrated circuit memory device includes a test pattern data generator circuit that is configured to generate an extended test pattern data based on test pattern data provided to the memory device during a test mode of the memory device and is configured to provide the extended test pattern data and the test pattern data during a test mode of the memory device. Related methods are also disclosed.

 
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