Semiconductor integrated circuit compensating variations of delay time

   
   

A semiconductor device includes a first circuit and a second circuit cascaded therefrom, a pattern examination section for examining the input signal pattern for the first circuit to estimate a delay in the first circuit, a delay control block for controlling an internal source potential based on the estimated delay for controlling the source potential for the second circuit so that the signal delay from the second circuit has small variations of delay time. The integrated circuit can be formed on a reasonable specification, and achieves a lower dissipation and a higher reliability.

 
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