Low power reduced voltage swing latch

   
   

An improved clocking circuit is provided for generating a half swing clock. Previous circuit operations required an additional supply voltage rail (Vdd/2), but the preferred embodiment exploits charge sharing to generate a half swing clock with less power and without the additional supply voltage rail. To drive clock nodes to Vdd/2, a shunt transistor is opened, and the fully charged clock node shares its charge with the fully discharged clock node. When capacitances have been properly matched, both nodes will settle at Vdd/2.

 
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