Memory controller and a cache for accessing a main memory, and a system and a method for controlling the main memory

   
   

A memory control system has a replacement detection/notification circuit for detecting occurrence of replacement of dirty entry in a cache and informing a memory controller of the detection, and a state control circuit for precharging the currently active page in a main memory when the memory controller is informed of the detection and a preceding access to the main memory attendant upon the replacement of dirty entry is completed. By precharging the active page in the main memory to return to the idle state when the preceding access attendant upon the replacement of dirty entry is completed, the succeeding access can be done only by activating the aimed page probably different from the above page. It is thereby obviated to return the activated page due to the preceding access to the idle state after a page miss occurs in the succeeding access.

 
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