A trimming circuit includes a signal separation circuit for separating an
input signal into a clock signal, a reset signal, a data signal, and a
memory writing voltage signal in accordance with voltage levels. The
memory circuit in the trimming voltage control circuit has at least first
and second different error correction circuits. The first error correction
circuit has a higher error correction capability but lower
input-per-output bit efficiency than the second error correction circuit
to correct important data such as a highest bit inputted to a D/A
converter. The second error correction circuit such as SEC has a higher
input-per-output bit efficiency than the first error correction circuit to
correct data with an error correction code. The lowest or second lowest
input bits are directly supplied to the D/A converter without error
correction.
