Method and apparatus for transparent cascading of multiple content addressable memory devices

   
   

A CAM system includes two or more CAM devices having the same device identification number (DID). One or more priority address bits indicating priority between the CAM devices may be assigned to each CAM device. Each CAM device may receive a mode signal indicating whether the CAM device operates independently or in cooperation with other cascaded CAM devices. During compare operations, each CAM device generates a highest priority match (HPM) index. A selected number of the priority address bits are inserted between the DID and the HPM index to form a device index for the system. During read and write operations, a first portion of an input address is used to select a row of CAM cells in each CAM device. A second portion of the input address is compared to a selected number of the priority address bits to enable an array in one of the CAM devices.

 
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