A Packet Processor for a communication apparatus, for processing received
and transmitted data streams made of packets. Each packet includes a
header and a payload section, which includes a receiving part, a
transmitting part, a Backbone Bus for conveying management data,
instructions and addresses between various components of the Packet
Processor, and a timing and control unit for administering the operation
of the Packet Processor, and for timing of using transmission slots for
the transmit path. The receiving part includes a receiving PHY interface
by which a flow of data stream is conveyed from a Modulator-Demodulator
section of the modem to the Packet Processor. The receiving part further
includes a receiving Tubular Bus which received the flow of data stream,
conveyed from the modem to the Packet Processor, the receiving Tubular Bus
conveys data, while processed, the direction from the receiving PHY
interface to a host interface. The receiving part includes one or more
processing units between sections of the first Tubular Bus for
sequentially receiving portions of a data stream from a section of the
Tubular Bus, processing it and outputting the processed data to a next
section of the first Tubular Bus. The receiving part contains a FIFO
storage unit before and a FIFO storage unit after any of the processing
units on the receiving Tubular Bus, for providing a temporary storage for
portions of the data stream, and a first host interface for receiving data
from the receiving Tubular Bus and conveying it to a host. The
transmitting part further includes a FIFO storage unit before and after
any of the processing units on the second Tubular Bus, and a transmitting
PHY interface for receiving processed data from the transmitting Tubular
Bus and conveying it to a Modulator-Demodulator section.
