Performing a hash algorithm in a processor architecture to alleviate performance bottlenecks and improve overall algorithm performance. In one embodiment of the invention, the hash algorithm is pipelined within the processor architecture.

 
Web www.patentalert.com

< System and method for traversing a firewall with multimedia communication

< Apparatus and method for cryptographic key expansion

> Crypto-synchronization for secure communication

> Systems and methods for hiding a data group
~ 00619