An input signal is compared to 2.sup.N-1 reference voltages to generate 2.sup.N-1 corresponding binary valued comparison signals, delaying at least one of the comparison signals by a variable delay and detecting a difference in arrival time between the delayed signal and another comparison signal. A time interpolation signal encoding a plurality of bins within a least significant bit quantization level is generated, based on the detected difference in arrival time. An M-bit output data is generated based on the comparison signals and the time interpolation signal. A non-uniformity of a code density of the M-bit output data is detected, and based on the detecting the delaying is varied.

 
Web www.patentalert.com

< A/D convertion controlling device and image forming apparatus

< Flash A/D converter

> Dual-use comparator/op amp for use as both a successive-approximation ADC and DAC

> Self tracking ADC for digital power supply control systems

~ 00614