A power semiconductor IC device is disclosed. In one embodiment, the device includes a substrate, and a layer structure formed on the substrate. The layer structure includes a metallization layer including copper, wherein the metallization layer is formed as a stack structure including at least two copper layers and a stabilization layer between the two copper layers.

 
Web www.patentalert.com

< Optimization of electronic package geometry for thermal dissipation

< Device having a bonding structure for two elements

> Semiconductor chip with reinforcement structure

> Alignment devices and methods for providing phase depth control

~ 00614