Disclosed is an apparatus for controlling an enable interval of a signal controlling an operation of data buses which connect a bit line sense amplifier with a data sense amplifier according to a variation of an operational frequency of a memory device. The apparatus comprises a pulse width control section for changing the pulse width of an input signal depending on the operational frequency of the memory device after receiving the input signal, a signal transmission section for buffering a signal outputted from the pulse width control section, and an output section for receiving a signal outputted from the signal transmission section so as to output a first signal for controlling the signal to control the operation of the data buses.

 
Web www.patentalert.com

< System and method for separating attached field emission structures

< Random access memory employing read before write for resistance stabilization

> External beam expander

> Memory device, memory controller and memory system

~ 00612