Disclosed is a method, system, and computer program product for performing edge optimization on an electronic design. According to some approaches, the number of edges and/or the length of edges within an IC design are configured for optimized manufacturability and yield of an integrated circuit. The edge optimization may occur in real-time during layout, placement, and/or routing, or occur in a post-optimization step.

 
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< Designated MOSFET and driver design to achieve lowest parasitics in discrete circuits

< Efficient large-scale full-wave simulation

> Circuit element function matching despite auto-generated dummy shapes

> Embedded Test I/O Engine

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