A system and method to optimize multi-core microprocessor performance using voltage offsets is presented. A multi-core device tests each of its processor cores in order to identify each processor core's optimum supply voltage. In turn, the device configures voltage offset networks for each processor core based upon each processor core's identified optimum supply voltage. As a result, the offset voltages produced by the voltage offset networks are subtracted from the multi-core device's main voltage, which results in the voltage offset networks supplying optimum supply voltages to each processor core. The voltage offset networks may include fuses to generate a fixed voltage offset, or the voltage offset networks may include a control circuit to dynamically adjust voltage offsets during the multi-core device's operation.