A non-volatile memory cell array and associated method of use are disclosed. In accordance with various embodiments, the array includes a plurality of programmable resistive sense elements (RSEs) coupled to a shared switching device. The switching device has a common source region and multiple drain regions, each drain region connected to an associated RSE from said plurality of RSEs.

 
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< RESISTIVE SENSE MEMORY ARRAY WITH PARTIAL BLOCK UPDATE CAPABILITY

< VOLTAGE REFERENCE GENERATION FOR RESISTIVE SENSE MEMORY CELLS

> Bidirectional Non-Volatile Memory Array Architecture

> DOUBLE SOURCE LINE-BASED MEMORY ARRAY AND MEMORY CELLS THEREOF

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