A bidirectional memory array architecture for non-volatile memory is disclosed. In accordance with some embodiments, a plurality of memory cells are arranged into an M number of rows and an N number of columns with each memory cell having a resistive sense element (RSE) and a switching device. A total number of M+N+1 control lines extend adjacent to and are connected with the memory cells to facilitate bi-directional programming of resistive states to each memory cell.

 
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< VOLTAGE REFERENCE GENERATION FOR RESISTIVE SENSE MEMORY CELLS

< Non-Volatile Memory Cell with Multiple Resistive Sense Elements Sharing a Common Switching Device

> DOUBLE SOURCE LINE-BASED MEMORY ARRAY AND MEMORY CELLS THEREOF

> Optical Waveguide With Reflector

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