An apparatus and method for controlling a memory interface are provided. The apparatus includes a memory controller controlling a memory and a clock generator applying a system bus clock signal and a memory clock signal to the memory controller. The memory controller applies a memory clock signal having a frequency higher than the frequency of the system bus clock signal to the memory. Accordingly, a high data transfer bandwidth can be obtained with the same cost and effort as for manufacturing a conventional system-on-chip (SOC) while using a memory having a high operating speed.