A method for connecting a first and second component in a logic device is disclosed. A path is generated between the first and second components with an appropriate amount of delay to satisfy short-path timing constraints that define a minimum delay on the path. A first interconnect line from a plurality of interconnect lines and a second interconnect line to connect with the first interconnect line sub-optimally from a delay minimization perspective are selected in order to satisfy the short-path timing constraints.

 
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