A semiconductor memory device comprise a word line, a bit line intersecting the word line, a memory element arranged at intersections of the word line and the bit line and having different required time for a write operation according to a logical value of write data, a write driver supplying a write current to the bit line, a write control circuit controlling operations of the write driver, and a timing signal generation circuit supplying a timing signal to the write control circuit. The timing signal has a waveform including a pulse indicating a time of starting supplying the write current when a first logical level is to be written, a pulse indicating a time of ending supplying the write current if the first logical level is to be written, and a pulse indicating one of a time of starting supplying the write current and a time of ending supplying the write current when a second logical level is to be written.