In an example embodiment, there is a method for packaging an integrated circuit device (IC) having a circuit pattern (305) in a wafer-level chip-scale (WLCS) package (300). The method includes depositing a metal layer (5, 10, 15) on a first dielectric layer (315) and filling (20) in bond pad openings (310) and bump pad openings (330); the metal layer (360) has atop (340) and bottom (360) layer. In the metal layer (360), bond pad connections (310) and bump pad connections (330) are defined (25, 30) by removing the top layer of metal in areas other than at bond pad openings (310) and bump pad openings (330), and leaving the bottom layer (360) of metal in areas without bond pad or bump pad connections. In the bottom metal layer, connection traces between the bond pad and bump pad are defined (35, 40). A second organic dielectric layer (325) is deposited (45) on the silicon substrate (305), enveloping the circuit pattern. The second organic dielectric layer is removed (50) from the bump pad connections exposing the bump pads (330).