A wafer level semiconductor package includes a semiconductor chip having a circuit part. A bonding pad group is disposed in the semiconductor chip and included in the bonding pad group is a power pad that is electrically connected to the circuit part. An internal circuit pattern is disposed at a side of the bonding pad group. An additional power pad is disposed at a side of the bonding pad group, and the additional power pad is electrically connected to the circuit part. An insulation layer pattern is disposed over the semiconductor chip, and the insulation layer includes openings that expose the power pad, the internal circuit pattern, and the additional power pad. A redistribution is disposed over the insulation layer pattern, and the redistribution is electrically connected to at least two of the power pad, the internal circuit pattern, and the additional power pad.