A multiplexed hierarchical array of interrupt controllers is configured to enable low latency task switching of a processor. The hierarchical array comprises a plurality of interrupt controllers coupled to a root interrupt controller. For each task that the processor is configured to execute, a corresponding interrupt controller is provided. To switch the processor to a task, the corresponding interrupt controller signals the root interrupt controller which, in turn, sends an interrupt and a Task Identifier to the processor. The root interrupt controller also cooperates with an access multiplexer/demultiplexer to select the corresponding interrupt controller for communication with the processor. By providing interrupt controller selection as well as task identification, the hierarchical array offloads arbitration and context switching overhead from the processor. That is, in response to the interrupt, the processor switches to the identified task and may access a memory address space dedicated to the task.