A DC-DC converter reducing reversed current in a low load state and increasing output voltage response speed. An error amplification circuit generates an error signal from the output voltage. A pulse signal generation circuit generates a first pulse signal in accordance with the error signal. A comparison circuit generates a comparison result signal from the error signal. A drive signal generation circuit generates a constant level signal and a second pulse signal. An output circuit receives the first pulse signal and either the constant level signal or the second pulse signal to generate first and second drive signals for driving first and second transistors. The output circuit generates the second drive signal in accordance with the first pulse signal when receiving the constant level signal and generates the second drive signal with the first and second pulse signals when receiving the second pulse signal.