There is provided a semiconductor memory device including; first and second active areas formed to extend in a first direction on a semiconductor substrate, first and second split word lines formed in a second direction on the semiconductor substrate, a common source line extending between the first and second active areas in the first direction and coupled to the first and second active areas, a first variable resistance element formed on the first active area between the first and second split word lines, a second variable resistance element formed on the second active area between the first and second split word lines, first and second bit lines extending in the first direction and respectively coupled to the first and second variable resistance elements.

 
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< Metal carbide gate structure and method of fabrication

> Analyte stages including tunable resonant cavities and Raman signal-enhancing structures

> NAND memory with side-tunneling

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