A control logic detects voltage regulator failure in a power supply. The control logic comprises first and second lines configured for respective connection to a controller node and a phase node of a voltage regulator, a delay element coupled to the first line configured to delay signals at the controller node into alignment with signals at the phase node, and a level detector coupled to the second line configured to convert the signals at the phase node into at least two digital representations indicative of respective signal thresholds. A logic compares timing of the delayed signals with the digital representations and detects occurrence of a voltage regulator fault based on the timing comparison.