A method for centralized dynamic link configuration (CDLC), performed by a processor and a chipset is provided. In the method, the processor first notifies the chipset of CDLC enablement. The chipset then issues a command to the processor after receiving notification of CDLC enablement. The processor broadcasts a preparation completion signal after receiving the command. The chipset asserts a signal and activates a timer to start counting after receiving the preparation completion signal. The processor configures devices of the processor, corresponding to a bus, according to one of multiple sets of first link management mode (LMM) configuration parameters in a first LMM register of the processor, indicated by first link management action field (LMAF) code in a first LMAF register of the processor, after detecting that the signal is asserted. The chipset configures devices of the chipset, corresponding to the bus, according to one of multiple sets of second LMM configuration parameters in a second LMM register of the chipset, indicated by second LMAF code in a second LMAF register of the chipset, when asserting the signal. The chipset de-asserts the signal when the timer reaches a predetermined value.