A mesochronous clock system and method to minimize latency and buffer requirements for data transfer in a large multiprocessor computing system. A stream of data is transferred from a first clock domain with a first clock signal to a second clock domain with a second clock signal. The first and second clock signals have a mesochronous relationship. The first clock signal is sampled in the second clock domain. In response to the sampling of the first clock signal, a modified version of the first clock signal is formed having a known phase relationship to the second clock signal. A parallel form of the received data is formed under the control of modified version of the first clock signal. In response to the sampling of the first clock signal, a subset of contiguous bits of the parallel data is selected for use in the second clock domain.

 
Web www.patentalert.com

< Processor with configurable association between interface signal lines and clock domains

> Network router configured for executing network operations based on parsing XML tags in a received XML document

> Dual-component state token with state data direct access index for systems with high transaction volume and high number of unexpired tokens

~ 00593