A register system for a data processor which operates in a plurality of
modes. The register system provides multiple, identical banks of register
sets, the data processor controlling access such that instructions and
processes need not specify any given bank. An integer register set
includes first (RA[23:0]) and second (RA[31:24]) subsets, and a shadow
subset (RT[31:24]). While the data processor is in a first mode,
instructions access the first and second subsets. While the data
processor is in a second mode, instructions may access the first subset,
but any attempts to access the second subset are re-routed to the shadow
subset instead, transparently to the instructions, allowing system
routines to seemingly use the second subset without having to save and
restore data which user routines have written to the second subset. A
re-typable register set provides integer width data and floating point
width data in response to integer instructions and floating point
instructions, respectively. Boolean comparison instructions specify
particular integer or floating point registers for source data to be
compared, and specify a particular Boolean register for the result, so
there are no dedicated, fixed-location status flags. Boolean
combinational instructions combine specified Boolean registers, for
performing complex Boolean comparisons without intervening conditional
branch instructions, to minimize pipeline disruption.