A memory device includes an interface controller for communication with a semiconductor device over a communication link. A clock signal is transmitted from the semiconductor device over the link to the memory device. A frequency of the clock signal may be any within a given range of frequencies. A frequency value signal conveying the value of the frequency of the clock signal is also transmitted. The interface controller includes circuitry for deriving from the clock signal and from the frequency value signal at least one timing signal for any operation in the memory device.