A method for operating a processor in data processing system comprises: asserting a debug control signal to cause the processor to enter a debug operating mode; initializing a plurality of shared processor resources with debug configuration information, wherein the plurality of shared processor resources are shared between a normal operating mode and the debug operating mode; executing instructions with the processor while in the debug operating mode; re-initializing the processor in response to a reset event; and preventing the reset event from re-initializing a predetermined portion of the debug configuration information in the plurality of shared processor resources. This allows processor debugging through reset events without losing the debug information.

 
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> Memory and multi-state sense amplifier thereof

> Memory storage devices comprising different ferromagnetic material layers, and methods of making and using the same

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