An interface circuit is connected to an ATE via a test control bus BUS3
that differs from main buses, receives a control signal output from the
ATE, and controls multiple BIST circuits according to the control signal.
Furthermore, a DUT is configured such that a test result signal specified
by the control signal can be read by the ATE via the test control bus. A
BISI synchronous control unit generates a first control signal for
individually controlling the multiple BIST circuits included in the DUT,
and a second control signal for reading the test result signal generated
by the BIST circuit, and supplies these signals to the DUT via the test
control bus.