A digital system including flash memory, coupled to a system-on-a-chip within which a flash memory subsystem controller is embedded, is disclosed. The system-on-a-chip includes support for a standard external interface, such as a Universal Serial Bus (USB) or IEEE 1394 interface, to which a host system such as flash memory test equipment can connect. Initialization of the flash memory is effected by opening a communications channel between the host system and the embedded flash memory subsystem controller. The host system can then effect initialization of the flash memory subsystem, including formatting of the flash memory arrays, loading application programs, and the like, over the communications channel.

 
Web www.patentalert.com

< DIAGNOSTIC MECHANISM IN DIFFERENTIAL PRESSURE TYPE MASS FLOW CONTROLLER

> DISK DRIVE HAVING A HEAD LOADING/UNLOADING RAMP THAT INCLUDES A TORSIONALLY-COMPLIANT MEMBER

> SWITCHABLE ACCESS STATES FOR NON-VOLATILE STORAGE DEVICES

~ 00587