The present disclosure relates to memory arrays with read reference voltage cells. In particular the present disclosure relates to variable resistive memory cell apparatus and arrays that include a high resistance state reference memory cell and a low resistance state reference memory cell that provides a reliable average reference voltage on chip to compare to a read voltage of a selected memory cell and determine if the selected memory cell is in the high resistance state or low resistance state. These memory arrays are particularly suitable for use with spin-transfer torque memory cells and resolves many systematic issues related to generation of a reliable reference voltage.

 
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< VARIABLE WRITE AND READ METHODS FOR RESISTIVE RANDOM ACCESS MEMORY

> MEMORY DEVICE STRUCTURES INCLUDING PHASE-CHANGE STORAGE CELLS

> SYSTEM AND METHOD OF MANAGING MEMORY

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