A method and mechanism for controlling threads in a multithreaded
multicore processor. A processor includes multiple cores, each of which
are capable of executing multiple threads. A control register which is
shared by each of the cores is utilized to control the status of the
threads in the processing system. In one embodiment, the shared register
includes a single bit for each thread in the processor. Depending upon
the value written to a bit of the shared register, one of three results
may occur with respect to a thread which corresponds to the bit. In one
embodiment, writing a "0" to a bit of the shared register will cause a
corresponding thread to be Parked. Writing a "1" to a bit of the shared
register will cause a corresponding thread to either be UnParked or be
Reset. Whether writing a "1" to a bit of the register causes the
corresponding thread to be UnParked or Reset depends upon a state of the
processor.