A method, apparatus and system of a self-test output for high density BIST are disclosed. In one embodiment, an integrated circuit includes one or more memories, a BIST controller coupled to the one or more memories to perform write operation and to receive a PASS/FAIL signal from each embedded memory and one or more comparators coupled to the one or more memories latch mutually identical outputted data coming from the memories upon a rising edge of an ORDY signal. In addition, the comparators may compare the latched mutually identical outputted data and output associated PASS/FAIL signal to the BIST controller. The BIST controller registers the received PASS/FAIL result upon receiving the PASS/FAIL signal from the comparators. The integrated circuit may include output registers coupled to the BIST controller and the comparators output a data log substantially serially upon receiving a SHIFT/CLK signal from the BIST controller.