An instruction execution pipeline for use in a data processor. The instruction execution pipeline comprises: 1) an instruction fetch stage; 2) a decode stage; 3) an execution stage; and 4) a write-back stage. The instruction pipeline repetitively executes a loop of instructions by fetching and decoding a first instruction associated with the loop during a first iteration of the loop, storing first decoded instruction information associated with the first instruction during the first iteration of the loop, and using the stored first decoded instruction information during at least a second iteration of the loop without further fetching and decoding of the first instruction during the at least a second iteration of the loop.