A PRAM and method of forming the same are disclosed. In various embodiments, the PRAM includes a lower insulation layer formed on a semiconductor substrate, a phase change material pattern formed on the lower insulation layer and a heating electrode contacting the phase change material pattern. The heating electrode can be formed of a material having a positive temperature coefficient such that specific resistance of the material increases as a function of temperature.

 
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> Ferroelectric random access memories (FRAMS) having lower electrodes respectively self-aligned to node conductive layer patterns and methods of forming the same

> Protection of three dimensional transistor structures during gate stack etch

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