A technique that improves both processor performance and associated data
bandwidth through user-defined interfaces that can be added to a
configurable and extensible microprocessor core. These interfaces can be
used to communicate status or control information and to achieve
synchronization between the processor and any external device including
other processors. These interfaces can also be used to achieve data
transfer at the rate of one data element per interface in every clock
cycle. This technique makes it possible to design multiprocessor SOC
systems with high-speed data transfer between processors without using
the memory subsystem. Such a system and design methodology offers a
complete shift from the standard bus-based architecture and allows
designers to treat processors more like true computational units, so that
designers can more effectively utilize programmable solutions rather than
design dedicated hardware. This can have dramatic effects not only in the
performance and bandwidth achieved by designs, but also in the time to
market and reuse of such designs.