A CMOS integrated circuit includes a substrate having an NMOS region with a P-well and a PMOS region with an N-well. A shallow trench isolation (STI) region is formed between the NMOS and PMOS regions and a composite silicon layer comprising a strained SiGe layer is formed over said P well region and over said N well region. The composite silicon layer is disconnected at the STI region. Gate electrodes are then formed on the composite layer in the NMOS and PMOS regions.