A semiconductor metal structure with an efficient usage of the chip area is provided. The structure includes a substrate, a copper-based interconnection structure over the substrate, the copper-based interconnection structure comprising a plurality of metallization layers connected by vias and in first dielectric layers, at least one aluminum-based layer over and connected to the copper-based interconnection structure, wherein a top layer of the at least one aluminum-based layer comprises a bond pad and an interconnect line connecting to two underlying vias, vias/contacts connecting a top layer of the copper-based interconnection structure and a bottom layer of the at least one aluminum-based layer, wherein the vias/contacts are in a second dielectric layer, and a third dielectric layer overlying the at least one aluminum-based layer, wherein the bond pad is exposed through an opening in the third dielectric layer.