A method for processing an integrated circuit is provided. The method
includes providing a first integrated circuit having a first scale,
wherein the first integrated circuit comprises a shrinkable circuit
comprising a first intellectual property (IP) layout, and a
non-shrinkable circuit comprising a second IP layout; and generating a
second integrated circuit having a second scale smaller than the first
scale. The step of generating the second integrated circuit includes
shrinking the shrinkable integrated circuit to the second scale. The
method further includes merging the second IP layout with the
non-shrinkable circuit to generate a final integrated circuit.