A processor is disclosed herein that may execute an instruction that
includes an immediate value and a reference to a register accessible to
the processor. The instruction causes the processor to perform a test
using the immediate value and the contents of the register referenced in
the instruction. Based on the outcome of test, the subsequent instruction
is executed or skipped. Further, the instruction includes at least one
bit that specifies how the test is to be performed. The bit may specify
that the immediate value is to be compared to the register value, or that
the immediate value is used to mask the register value and the masked
register value has one or more of its bits tested.