A data inversion register technique for integrated circuit memory testing
in which data input signals are selectively inverted in a predetermined
pattern to maximize the probability of identifying failures during
testing. In accordance with the technique of the present invention, on
predetermined input/outputs (I/Os,) data inputs may be inverted to create
a desired test pattern (such as data stripes) which are "worst case" for
I/O circuitry or column stripes which are "worst case" for memory arrays.
A circuit in accordance with the technique of the present invention then
matches the pattern for the data out path, inverting the appropriate data
outputs to obtain the expected tester data. In this way, the test mode is
transparent to any memory tester.