A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transistor.

 
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> Apparatus and method for imaging with surface enhanced coherent anti-stokes raman scattering (SECARS)

> Dynamic surface annealing of implanted dopants with low temperature HDPCVD process for depositing a high extinction coefficient optical absorber layer
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